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#verilog

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OK this is pretty cool. A project called DigitalJS can give you a visual layout of all of the logic that'll go into a Verilog design, using Yosys to do the generation. Being able to see what's being ultimately produced helps me, a much more visual person, understand when I've flubbed something that generates too much logic. I already optimized one piece of the display RAM using it. It's at digitaljs.tilk.eu/ but you can also run it locally. #fpga #verilog #ulx3s

Hey all! I'm due for an (re-)introduction: I'm Jack, an engineer in the NYC area from a firmware & cybersecurity background, currently working in something like hardware-software co-design.

Technical work is often with #rust #kicad #python #verilog #c, and in all-too-rare moments stuff like #haskell #forth #agda and #prolog

I've never been much for social media, usually preferring to keep interests local: a better-detailed #introduction to follow as I figure this out 🙂

The #RTL / #Verilog folks at work have started using the term "API" like they're children who got it for Christmas.

First a ticket that uses "API" six times, three of them in the same sentence, and none adding any meaning to the text.

Now a chap who insists that he needs a way to "rebuild the API", without explaining what, exactly, it is that he's trying to build.

It seems 2024 is the #Year of the #API, as a magic #buzzword that makes you more credible when talking to #software folks.